The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Devices such as computers, mobile phones, tablets, etc. typically include a system-on-chip (SoC). FIG. 1 shows an example of a device 10 that includes a SoC 12 and one or more dynamic random access memories (DRAMs) 14. The DRAMs 14 can be implemented as one or more integrated circuits that are connected to but separate from the SoC 12. The device 10 can also include one or more storage drives 16 connected to ports 17 of the SoC 12. The storage drives 16 can include flash memory, solid-state drives, hard disk drives, and/or hybrid drives. A hybrid drive includes a solid-state drive with solid-state memory and a hard disk drive with rotating storage media.
The SoC 12 can include one or more image processing devices 20, a system bus 22 and a memory controller 24. Each of the image processing devices 20 can include, for example: a control module 26 with a central processor (or central processing unit (CPU)) 28; a graphics processor (or graphics processing unit (GPU)) 30; a video recorder 32; a camera image signal processor (ISP) 34; an Ethernet interface such as a gigabit (Gb) Ethernet interface 36; a serial interface such as a universal serial bus (USB) interface 38 and a serial advanced technology attachment (SATA) interface 40; and a peripheral component interconnect express (PCIe) interface 42. The image processing devices 20 access the DRAMs 14 via the system bus 22 and the memory controller 24. The DRAMs 14 are used as main memory. For example, one of the image processing devices 20 provides a physical address to the memory controller 24 when accessing a corresponding physical location in one of the DRAMs 14. The image processing devices 20 can also access the storage drives 16 via the system bus 22.
The SoC 12 and/or the memory controller 24 can be connected to the DRAMs 14 via one or more access ports 44 of the SoC 12. The DRAMs 14 store user data, system data, and/or programs. The SoC 12 can execute the programs using first data to generate second data. The first data can be stored in the DRAMs 14 prior to the execution of the programs. The SoC 12 can store the second data in the DRAMs 14 during and/or subsequent to execution of the programs. The DRAMs 14 can have a high-bandwidth interface and low-cost-per-bit memory storage capacity and can handle a wide range of applications.
The SoC 12 includes cache memory, which can include one or more of a level zero (L0) cache, a level one (L1) cache, a level two (L2) cache, or a level three (L3) cache. The L0-L3 caches are arranged on the SoC 12 in close proximity to the corresponding ones of the image processing devices 20. In the example shown, the control module 26 includes the central processor 28 and L1-L3 caches 50. The central processor 28 includes a L0 cache 52. The central processor 28 also includes a memory management unit (MMU) 54, which can control access to the caches 50, 52.
As the level of cache increases, the access latency and the storage capacity of the cache increases. For example, L1 cache typically has less storage capacity than L2 cache and L3 cache. However, L1 cache typically has lower latency than L2 cache and L3 cache.
The caches within the SoC 12 are typically implemented as static random access memories (SRAMs). Because of the close proximity of the caches to the image processing devices 20, the caches can operate at the same clock frequencies as the image processing devices 20. Thus caches exhibit shorter latency periods than the DRAMS 14.
The number and size of the caches in the SoC 12 depends upon the application. For example, a handset (or mobile phone) may not include an L3 cache and can have smaller sized L1 cache and L2 cache than a personal computer. Similarly, the number and size of each of the DRAMs 14 depends on the application. For example, mobile phones currently have 1-4 gigabytes (GB) of DRAM, personal computers currently have 4-16 GB of DRAM, and servers currently have 32 GB-512 GB of DRAM. In general, cost increases as the amount of DRAM increases.
In addition to the cost of DRAM, it is becoming increasingly more difficult to decrease the package size of DRAM for the same amount of storage capacity. Also, as the size and number of DRAMs incorporated in a device increases, the capacitances of the DRAMs increase, the number and/or lengths of conductive elements associated with the DRAMs increase, and buffering associated with the DRAMs increases. In addition, as the capacitances of the DRAMs increase, the operating frequencies of the DRAMs decrease and the latency periods of the DRAMs increase.
During operation, programs and/or data are transferred from the DRAMs 14 to the caches in the SoC 12 as needed. These transfers have higher latency as compared to data exchanges between (i) the caches, and (ii) the corresponding processors and/or image processing devices. For this reason, accesses to the DRAMs 14 are typically avoided due to the longer latency periods.
During boot up, programs can be transferred from the storage drives 16 to the DRAMs 14. For example, the central processor 28 can transfer programs from the storage drive 16 to the DRAMs 14 during the boot up. During the boot up, the central processor 28 can attempt to access data stored in the DRAMs 14. The percentage of hits associated with this access attempt may initially be near or equal to 0%. However, the percentage of hits approach 100% by the end of the boot up.